Semiconductor technologies have continued to use smaller geometries to allow more circuitry on each integrated circuit product. As the geometries used to produce integrated circuit chips become smaller, the size of the silicon die becomes smaller, the products become faster and their unit cost decreases. Additionally, operating voltages decrease resulting in less overall power and leakage becomes a large proportion of total product power.
In technologies with larger geometries, leakage comprised such a small part of the total power that many products used leakage screens solely as a defect screen. Leakage monitoring in manufacturing lines assessed only the subthreshold component of leakage. In newer technologies, products are screened to limits that match the leakage models provided to customers with corresponding yield loss. While subthreshold leakage is still the predominate cause of leakages, other mechanisms such as gate leakage significantly contribute to overall product leakage and overall product power. Since the contribution of subtheshold leakage and gate leakage vary as a function of the device types used to build circuits in semiconductor products, it is important to identify the source of the leakage so that it can be controlled in the manufacturing process.
Current methods used to predict chip leakage have addressed the problem of leakage by calculating a chip's total leakage. This has traditionally been done by determining the number of times a device type occurs and multiplying that number by the estimated leakage for that type of device. This leakage estimation is determined under test conditions and is correlated to a few scribe line measurements using a one time set of manufacturing hardware. Using this calculation, the leakage of a single chip can be determined, however, a determination of how that single chip's leakage relates to other chips that are to be built using the library elements, or how the leakage will vary as the source of the leakage changes from subthreshold leakage to gate leakage, is unknown.
One of the problems with the current methods of predicting chip leakage is that there is no way to identify the source of the leakage, e.g., if it is subthreshold leakage or gate leakage. This is particularly important because subthreshold leakage and gate leakage behave differently as temperature changes. Furthermore, the temperature in which scribe line measurements are currently taken may be different than the actual temperature of the product while in use. Therefore, current methods do not evaluate how temperature impacts the amount of leakage that occurs within a chip. For example, a chip may be tested at temperatures ranging from 55-80° F. and have a total leakage of 35% of total power. However, in practice, that same chip may be used at temperatures upwards of 100-125° F., which may result in a total leakage of 65% of total power. Accordingly, the current methods of predicting chip leakage do not account for this type of variation.
Additional problems also exist with current methods for predicting chip leakage. For example, current methods do not consider chip variations that may occur as a result of shifting during the manufacturing process. These shifts may result in chips being offset such that the physical placement and distances between scribe lines on the chips vary from the tested chips. These inherent scribe-to-chip offsets may alter the topography of the chip and affect the type and amount of leakage that will be encountered by the chip as compared to the scribe line structures.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.